Digital Electronics
Explainer
D Flip-Flops and Clock Edges
Why does a register ignore its input except at one tiny instant?
Quick check · tap an answer to continue
Lesson notes
Key points
- A D flip-flop stores one bit, copying input D to output Q only on the active clock edge.
- A positive-edge flip-flop samples D at the instant the clock rises from zero to one.
- D must be stable for a setup time before the edge and a hold time after, or Q may become unreliable.
- Grouping n D flip-flops on one clock forms an n-bit register, the basic storage inside every processor.
Takeaway: A D flip-flop captures D at the clock edge: Q(next) = D.
Quick check: When does a positive-edge D flip-flop update Q?
- When clock goes 0 to 1
- Whenever D changes
- While clock stays high
Edge-triggered devices sample D only at the rising clock transition.
D flip-flopRising edgeSetup and holdRegister
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