Digital Electronics
Exam drill
Exam Drill: Ripple Counter Delay
This counter question costs students marks every year
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Lesson notes
Design synchronous counters with excitation tables and explain shift registers
Key points
- In a ripple counter, each flip-flop is clocked by the previous flip-flop's output.
- So the delays add up stage by stage instead of happening at once.
- Worst case is 1111 to 0000, where all four stages toggle in sequence.
- Total delay is 4 × 10 ns, which equals 40 ns.
Takeaway: Ripple counter delay = number of stages × flip-flop delay.
Quick check: A 4-bit ripple counter uses flip-flops with 10 ns delay. Worst-case settle time after a clock edge?
- 10 ns
- 40 ns
- 2.5 ns
State that propagation delay accumulates, then show n × tpd with units.
excitation tableasynchronous countershift register
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